1. Field of the Invention
The present invention relates to a package and a method thereof, and more particularly, to a lead frame lattice, a semiconductor package and a method thereof.
2. Background of the Related Art
As semiconductor package components are increasingly minimized in size, the size of a semiconductor package needs to be smaller and thinner for mass production. FIG. 1 illustrates a LOC (lead on chip) type semiconductor package. A paddle 1 is mounted on a semiconductor chip 2 on which, except at the center thereof, an adhesive cover film 4 is formed over a plurality of leads 3. Each lead has multiple bends. On the center of the surface of the chip 2, there are formed a plurality of chip pads 5, each of which is electrically connected by a metallic wire 6 to a corresponding one of the leads 3. An epoxy compound 7 is molded on the chip 2 including the leads 3, the adhesive film 4, the chip pads 5, and the metallic wires 6. The upper surface of a portion of each of the leads 3 is exposed externally.
With reference to FIGS. 2A through 2E, the fabrication method of the above chip-size semiconductor package will now be described. First, as shown in FIG. 2A, there is performed a die bonding process for mounting the semiconductor chip 2 on the paddle 1 extending from a die pad frame 8. As shown in FIG. 2B the die pad frame 8, which includes the chip 2 thereon is aligned with the lead frame 9 and fitted to the central padding. A welding process is performed to connect the die pad frame 8 to the lead frame 9.
As shown in FIG. 2B, a wire bonding process is performed with the metallic wires 6 to electrically connect each of the chip pads 5 formed on the central surface of the chip 2 to a corresponding one of the leads 3. As shown in FIG. 2C, the chip 2, connected by welding to each of the frames 8, 9, is aligned in a cavity 13 formed in the surface of a lower mold 12. Next, an upper mold 11 is attached to the lower mold 12 and a molding compound 7 is injected into a vent hole 12a.
As shown in FIG. 2D, the molds 11, 12 are detached from the frames 8, 9 after completing the molding process. A trimming process follows to cut off the externally projected portions from the molded package body 7, thereby completing the chip-size semiconductor package having externally exposed leads 3 from the bottom surface of the package body 7.
To fabricate the above semiconductor package, the semiconductor chip 2 is individually detached from a wafer prior to performing the die bonding. The detached chip 2 is sealingly aligned on the paddle 1 of the die pad frame 8 so as to proceed with the wire bonding process. However, the individual attachment of the chip to the paddle requires increased time due to the redundant and complicated fabrication steps. Also, the complicated steps may cause an external damage to the chip to thereby restrain its yield.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.